What is race around condition?How it is overcome in Master slave JK Flip flop?
person
brightness_auto
1 Answer
Race around condition :
i) In jk flip flop there occurs a condition called race around when we put both
j and k as 1.In race around Condition till the clock is high the output varies
continuously from 0 to 1 &1 to 0.
ii) This condition is undesirable as it is of no use because the change in output
is uncontrolled.
iii) In JK flip flop as long as clock is high for the input conditions J&K equals to
the output changes or complements its output from 1–>0 and 0–>1.
iv) This is called toggling output or uncontrolled changing or racing condition.
Consider above J&K circuit diagram as long as clock is high and J&K=11
then two upper and lower AND gates are only triggered by the
complementary outputs Q and Q(bar). I.e. in any condition according to
the propagation delay one gate will be enabled and another gate is
disabled.
v) If upper gate is disabled then it sets the output and in the next lower gate
will be enabled which resets the flip flop output.
vi) If the Clock On or High time is less than the propagation delay of the flip
flop then racing can be avoided. This is done by using edge triggering
rather than level triggering.
vii) If the flip flop is made to toggle over one clock period then racing can be
avoided. This introduced the concept of Master Slave JK flip flop.
i) In jk flip flop there occurs a condition called race around when we put both
j and k as 1.In race around Condition till the clock is high the output varies
continuously from 0 to 1 &1 to 0.
ii) This condition is undesirable as it is of no use because the change in output
is uncontrolled.
iii) In JK flip flop as long as clock is high for the input conditions J&K equals to
the output changes or complements its output from 1–>0 and 0–>1.
iv) This is called toggling output or uncontrolled changing or racing condition.
Consider above J&K circuit diagram as long as clock is high and J&K=11
then two upper and lower AND gates are only triggered by the
complementary outputs Q and Q(bar). I.e. in any condition according to
the propagation delay one gate will be enabled and another gate is
disabled.
v) If upper gate is disabled then it sets the output and in the next lower gate
will be enabled which resets the flip flop output.
vi) If the Clock On or High time is less than the propagation delay of the flip
flop then racing can be avoided. This is done by using edge triggering
rather than level triggering.
vii) If the flip flop is made to toggle over one clock period then racing can be
avoided. This introduced the concept of Master Slave JK flip flop.